LogicVision Introduces Embedded Test 4.0 -- Industry's First Product to Seamlessly Integrate Silicon Design, Debug and Manufacturing Test

Embedded Test 4.0 Significantly Reduces Time-To-Market and Test Costs

SAN JOSE, Calif.--(BUSINESS WIRE)--Feb. 25, 2002-- LogicVision, Inc., (Nasdaq:LGVN - news), a leading provider of embedded test for integrated circuits and systems, today introduced Embedded Test 4.0 (ET 4.0). This is the first product in the semiconductor industry that enables a chip designer to design hierarchical test capability and seamlessly reuse it for silicon debug and manufacturing test. ET 4.0 is the most comprehensive product introduced by LogicVision that extends capabilities familiar to LogicVision icBIST 3.X users, and creates the integrated infrastructure to enable time-efficient diagnostics and debug in a manufacturing environment.

Source: LogicVision
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"As the complexity of chips increases, IC testing will enhance our development metrics of new chip designs," said Mohan Yeghashankaran, National Semiconductor's vice president of product development. "We intend to use LogicVision's Embedded Test 4.0 as a seamless solution helping us with our test requirements through the integrated embedded test implementation and diagnostics approach."

"The costs associated with testing circuit designs, both ICs and printed circuit boards, are climbing. Greater functionality being packed into each design means the time required to test that design and the variety of different types of testing equipment needed to do so keep increasing," said Laurie Balch, Gartner Dataquest industry analyst, Technical Software. "The use of internal test methodologies will help maximize test coverage for designs, while minimizing both the pin count requirements for testers and the amount of time each design is tested. DFT-aware ATE hardware and software will further reduce manufacturing cycle times for steps such as wafer sort and final test."

Major features of Embedded Test 4.0 include:

• Structured framework for generation and sign-off of embedded test IP
• Vector-less transfer of test data from design to debug to manufacturing
• ATE independent user interfaces
• Real time hierarchical diagnostics for logic, memory, and PLLs
• Re-usability of embedded test IP throughout the life of the SoC

"This is the first known solution to successfully bridge the disciplines of IC design, IC diagnostics and characterization, and IC manufacturing test to create a seamless flow to system test," said Vinod Agarwal, LogicVision's president and CEO. "We believe LogicVision's Embedded Test 4.0 will help ensure accurate, highly efficient and cost-effective testing of complex SoCs, benefiting the entire semiconductor industry."

Unparalleled Ease of Use

Embedded Test 4.0 features automated test generation and ease-of-use. Simple flows are included for automatic generation and verification of embedded test IP, and for generation of test-ready embedded test databases. Through LV Workspace and ET Verify utilities, data is generated instantly, providing consolidated sign-off level design net lists, prepared test patterns and a test information database. Embedded test IP verification and sign-off provides a unified environment for fast design closure. Together, these features can dramatically reduce engineering effort and costs.

Integrated Design & Debug

With Embedded Test 4.0, ease of use doesn't end with the design engineers. LogicVision's ET 4.0 -- IC Debug executes directly on the tester and provides full access and control of all embedded test controllers within the chip under test. This interactive, ATE-independent diagnostics and characterization interface is unique among test products.

Embedded Test 4.0 also includes a LogicVision Database (LVDB) that generates manufacturing-ready test databases. LVDB collects all the necessary information to describe generated and contained embedded test IP for the SoC. This capability enables both vector-less hand-off from design to manufacturing and on-the-fly pattern generation at the tester. Each design or IP core generates an LVDB that can be read by another design, making hierarchy of test possible. Embedded Test 4.0 is unique in its ability to effectively handle design hierarchy with 3rd party IP, allowing tremendous savings to the user in both effort and time to market. The combination of vector-less hand-off, hierarchical test capability and interactive graphics user interface results in fast diagnostics, and fast turnaround, combined in a highly robust test solution to achieve the highest quality in a fraction of the time normally required.

The New World of Test

Embedded Test 4.0 offers comprehensive ease of use, resulting in dramatic time and cost saving, and unmatched silicon product quality. LogicVision's ET 4.0 elevates semiconductor test technology to the next level.

Availability

Embedded Test 4.0 is now available for Solaris and HP-UX operating system. For more product details and pricing, please contact LogicVision's sales offices via email at info@logicvision.com.

About LogicVision Inc.

LogicVision (Nasdaq:LGVN - news) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.

FORWARD LOOKING STATEMENTS:

Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected features and benefits of ET 4.0, such as reducing engineering effort and costs and silicon debug and diagnostics time, providing time-to-market value and helping users manage capital expense by extending the life of existing testers or enabling the use of lower cost testers, the anticipated benefits of internal test methodologies and DFT-aware ATE hardware and software, the intended use of the Company's products by and expected benefits to its customers, and the Company's belief that Embedded Test 4.0 will help ensure accurate, highly efficient and cost-effective testing of complex SoCs, thereby benefiting the entire semiconductor industry, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risk and uncertainties that could cause actual results to differ materially, including, but not limited to, developments in IC design and testing as well as the impact of alternative technological advances and competitive products, and other risks detailed in LogicVision's Prospectus dated October 31, 2001 filed with the SEC and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.

LogicVision, Embedded Test, LogicVision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.

ACRONYMS AND DEFINITIONS:

ATE:     Automatic Test Equipment
ATPG:    Automatic Test Pattern Generation
BIST:    Built-in-Self-Test
DFT:     Design-for-Test
EDA:     Electronic Design Automation
GDSII:   An industry format describing the physical structure of the
         chip design and used to create mask tooling for chip
         manufacturing.
GUI:     Graphics User Interface
HDL:     Hardware Description Language -- Describes the architecture
         and behavior of discrete electronic systems.
IC:      Integrated Circuit
RTL:     Register Transfer-Level -- A chip design language format --
         technology independent that can be Verilog or VHDL.
Verilog: A hardware description language used to design and
         document electronic systems.
VHDL:    VHSIC (Very High-Speed Integrated Circuit) HDL
IP:      Intellectual Property
SoC:     System-on-chip

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     LogicVision
     Clarisse Balistreri, 408/453-0146
     clarisse@logicvision.com
      or
     The Loomis Group (for LogicVision)
     Vincent Mayeda, 909/614-1767
     vincent@loomisgroup.com